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| RISCore32300TM Family System Controller Chip IDT79RC32134 Features RC32300-family System Controller - Direct connection between RC32364 and RC32134 - Up to 75 MHz operation - Drives latched address bus to memory and peripherals - Direct control of optional external data buffers - Programmable system watch-dog timers - Big or Little endian support x Interrupt Control - Provides services for internal and external sources - Allows status of each interrupt to be read and masked x Three general purpose 32-bit timer/counters x Programmable IO (PIO) - Input/Output/Interrupt source - Individually programmable x SDRAM/EDODRAM Controller (32-bit memory only) - 4 banks, non-interleaved, 256 MB total - Automatic refresh generation x UART Interface - Two 16550 Compatible UARTs - Baud rate support up to 1.5M x 8/16/32-bit boot PROM support x Boundary Scan JTAG Interface (IEEE Std. 1149.1 compatible) x Memory & Peripheral Controller - 6 banks, up to 8MB per bank x - 8/16/ or 32-bit interface per bank - Supports Flash ROM, SRAM, dual-port memory, and peripheral devices - Intel or Motorola style IO supports external wait-state generation x 4 DMA Channels - 4 general purpose DMA, each with Endianness swappers and byte lane data alignment - Any channel can be used for PCI - Supports memory-to-memory, memory-to-I/O,memory-toPCI, PCI-to-PCI, I/O-to-I/O transfers, and I/O support of scatter/gather - Supports chaining via linked lists of records - Supports unaligned transfers - Supports burst transfers - Programmable burst size x PCI Bridge - 32-bit PCI, up to 33 MHz - Revision 2.1 compliant - Target and master - Host or satellite - Three slot PCI arbiter, on-chip - Serial EEPROM support, for loading configuration registers x 3.3V core operation x 3.3V I/O operation with 5V tolerant I/O x 208 pin PQFP package Block Diagram CPU I/F Timer, UART, Interrupt Modules EDO/SDRAM Control Memory I/O Control Data & Address bus SDRAM/EDODRAM Control Memory & I/O Control DMA Channels RC32134 PCI I/F and Bridge PCI Bus The IDT logo is a registered trademark. RC64145, RC64474, RC64475, RC32134, RC4600, RC4640, RC4650, RC4700, RC3041, RC3051, RC3052, RC3081, RISController, and RISCore are trademarks of Integrated Device Technology, Inc. 1 of 25 2000 Integrated Device Technology, Inc. April 9, 2001 DSC 5602 IDT79RC32134 Description The IDT79RC32134 is a high performance system controller chip that supports IDT's RISCore32300 CPU family. The RC32134 offers a direct connection to IDT's RC32364 32-bit embedded microprocessor. The RC32134 provides the system logic for boot memory, main memory, I/O, and PCI. It also includes on-chip peripherals such as DMA channels, reset circuitry, interrupts, timers, and UARTs. Together, the RC32364 CPU and the RC32134 system controller form a complete CPU subsystem for embedded designs. Figure 1 illustrates the typical system implementation, based on the RC32364 CPU and the RC32134 system controller. The RC32134 interfaces directly to the RC32364 and provides all of the necessary control and address signals to drive the external memory and I/O. Note that, depending on the loading of the CPU data bus, external data buffers could be used to reduce the loading and isolate different memory regions. As illustrated in the system block diagram, the memory and I/O data path is external to the RC32134. and from the internal peripherals and registers is internal to the RC32134. Memory Controller. The Memory Controller on the RC32134 provides all of the address buses and control signals for interfacing the RC32364 CPU to standard SRAM, PROM, FLASH, and I/O and includes the boot PROM interface. The memory controller provides six individual chip selects and supports 8,16, and 32-bit wide memory and I/ Os. Two chip selects have highly configurable memory address ranges, allowing selection of various memory types and widths to be supported. The RC32134 provides controls for optional external data transceivers for systems that require fast signalling with large loads. SDRAM Controller. The SDRAM controller optimization provides higher throughput while using available DRAM technology. The SDRAM control register directly manages four banks of 32-bit physical non-interleaved memory. Each bank is 32-bits wide and supports a maximum of 64 MB per bank. Total memory support is 256 MB. The SDRAM controller has a built in refresh generator. EDO DRAM Controller. The RC32134 EDO DRAM Controller supports up to 4 banks of non-interleaved 32-bit wide EDO DRAMs. Most of the EDO DRAM pins are shared with the SDRAM controller, and as such, the two operations can not be simultaneously enabled. Selection between SDRAM or EDO DRAM is made at boot-time through system software operations. The EDO supports 256 MB total of EDO DRAM. The EDO controller has a built in refresh generator. PCI Interface. To transfer data between main memory and the PCI bus, the RC32134 incorporates a PCI interface. At reset time the PCI interface can be configured as either a host or satellite interface. The PCI interface supports 32-bit PCI at up to 33MHz and is PCI Specification, Revision 2.1 compliant. Device Overview The RC32134 interfaces directly to the RC32364's system bus. The RC32134 latches the address from the RC32364 internally and decodes it to detect which memory, I/O, or on-chip peripheral is being accessed, per the internal address map of the RC32134. The RC32134 generates all necessary control signals and address buses to the external memory and I/O. For main memory, I/O, on-chip peripherals, registers, and PCI, the RC32134 divides the physical address space into 14 different regions. The data path for the local memory and peripherals (with the exception of PCI) is external to the RC32134. The data path from the PCI bus RC32364 Clock RC32134 CPU I/F Serial PIO Timers, UART, Interrupt Ctl DMA Channels DRAM Ctl Memory & I/O Ctl Address & Control Memory & I/O SDRAM 32-bit Data Bus PCI Bridge with Arbiter 32-bit, 33Mhz PCI Bus Figure 1 System Block Diagram 2 of 25 April 9, 2001 IDT79RC32134 As a PCI master, the RC32134 can generate memory, I/O, or configuration cycles for direct local-to-PCI bus accesses. The PCI interface incorporates a 3-slot PCI bus arbiter, which includes fixed and round robin arbitration modes. As a PCI target, the RC32134 allows access to its internal registers and to the RISCore32300 local bus through the PCI I/O read and write, or Memory read and write commands. The RC32134 PCI interface supports swapping little endian data to big endian, when the CPU subsystem is configured as a big endian system. For more information on the PDCI interface, please refer to the PCI Specification, Revision 2.1. DMA Controller. Four general purpose DMA channels move data between source and destination ports. Source and destination ports can be system memory, PCI or I/O devices. Any of the four channels can be used for PCI initiator reads or writes. All four channels support a descriptor structure, to allow efficient data scatter/gather. The DMA controller supports swapping of data between big and little endian memory and I/O subsystems by memory region. It also supports quadword burst transfers. All external 16 and 8-bit memory I/Os are treated as memory-mapped, word-aligned devices. Expansion Interrupt Controller. The Expansion Interrupt Controller provides the interrupt logic for software to analyze the various RC32134 generated system interrupts and adds to the control already provided through the CP0 registers of the RC32364. Each system interrupt is registered and the pending status provided through this feature. The pending status can then be used to automatically generate a hardware interrupt to the CPU via individual mask bits. The pending interrupt status can also be optionally set or cleared by a direct software write. PIO. Programmable I/O (PIO) pins are provided on the RC32134 so that any unused peripheral pins can be programmed for use as general purpose discrete I/O pins. These PIO pins can be software programmed as bidirectional lines, allowing pin values to be software programmed in output mode and software readable while in the input mode. The PIO pins can also be used as a source of interrupts to the CPU. Maximum Interfacing flexibility is thus provided without requiring extensive modifications to the board. UART. The RC32134 incorporates two 16550 (an enhanced version of the 16450) compatible UARTs. To relieve the CPU of software overhead, the 16550 UART can be put into FIFO mode, allowing execution of either 16450 or 16550 compatible software. Two sets of 16-byte FIFOs are enabled during the 16550 mode: one set in the receive data path and one set in the transmit data path. A baud rate generator is included that divides the system clock by 1 to 64K and provides a 16X clock for driving the transmitter and receiver logic. Timers/Counters. Three on-chip 32-bit general purpose Timers are provided on the RC32134. Each timer consists of both a count and a compare register. The count register resets to zero and then counts upward until it equals the compare register. When the count and compare registers are equal, the TC_n output is asserted and the count is then reset to zero. JTAG. Board-level manufacturing debugging is facilitated through implementation of a fully compliant IEEE std. 1149.1 JTAG Boundary Scan interface. Thermal Considerations The RC32134 is guaranteed in a case temperature range of 0C to +90C, for commercial temperature devices; - 40C to +90C for industrial temperature devices. The speed (power) of the device and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. The equivalent allowable ambient temperature, TA, can be calculated using the thermal resistance from case to ambient (CA) of the given package. The following equation relates ambient and case temperatures: TA = TC - P * CA where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for the device. Typical values for CA at various airflows are shown in Table 1 CA Airflow (ft/min) 208 PQFP 0 18 200 14 400 11 600 9 800 8 1000 7 Table 1 Thermal Resistance (CA) at Various Airflows Revision History: July 21, 1999: Changed the following: Thermal Resistance values; Table 2, Pin Descriptions; Logic diagram - RC32134; Clock parameter temperature from 85 to 90 degrees; AC timing characteristics - RC32134; DC electrical characteristics; Power consumption - RC32134; Absolute maximum ratings diagram; Pin-out 208-PQFP table; RC32134 alternate signal functions. September 2, 1999: Corrected package drawing from 144-pin to 208-pin. November 1, 1999: Removed Maximum column from Power Consumption table. November 9, 1999: Moved pin 208 (sdram_245_oe_n) from Low drive to High drive in DC Electrical Characteristics Table. April 28, 2000: Added Mode Configuration Interface Reset Sequence figure on page 14. 3 of 25 April 9, 2001 IDT79RC32134 January 6, 2000: - Reordered Alternate Signals for the PIO Interface in Table 2 and changed pci_eeprom_mdi to pci_eeprom_mdo. - Switched alternate pin signals for pci_eeprom_mdo and pci_eeprom_mdi in PCI Interface section of Table 2. - Switched alternate pin signals for uart_rx and uart_tx in UART Interface section of Table 2. - In RC32134 Alternate Signal Functions table, changed pin designations under Alt #1 column for pins 22 - 29. - Changed 64145 references to 32134 in the Note section of the AC Timing Characteristics table. - Updated the User Manual Timing Diagram Reference column in the AC Timing Characteristics table. March 20, 2000: Changed PCI speed to 33 MHz. June 20, 2000: Values were revised for three local memory/peripheral bus signals in the AC Timing Characteristics table. July 12, 2000: Revised Tsu and Thld symbol numbers in UART section of AC Timing Characteristics table and revised reference to timing diagram. April 9, 2001: In the Local Memory/Peripheral bus section of the AC Timing Characteristics table, deleted cpu_coldreset_n associated with Tsu4. 4 of 25 April 9, 2001 IDT79RC32134 Pin Description Table The following table lists the pins provided on the RC32134. Note that several pins are multiplexed and have been assigned alternate functions. These pins are designated and defined accordingly throughout this table. Also note that those pin names followed by _n are active-low signals. Pin Name Type Alternate Signal(s) Description Local Memory and Peripheral Pins cpu_ad[31:0] I/O Not applicable CPU Address/Data Bus This is the RC32134's primary multiplexed and bidirectional address and data bus. The RC32134 latches this bus internally and uses it to generate the necessary address lines to the external memory and peripherals. If the transaction is a write, the CPU then drives data on cpu_ad(31:0). During CPU generated transactions, the CPU drives Address(31:4) into the cpu_ad bus, during its address phase. During DMA generated transactions (or RC32134 internal register reads), the address phase is unused and the chip drives data during a write. CPU LSB Address Bus During CPU generated transactions, the CPU drives Address(3:2) onto the cpu_addr bus. The RC32134 does not internally use the cpu_addr bus during the data phase. However, 8- or 16-bit memory or I/O systems must attach these two pins instead of mem_addr(3:2). CPU Address Latch Enable During CPU generated transactions, this signal indicates that the cpu_ad (31:0) is driving a valid address and can be latched internally by the RC32134. CPU Cycle In Progress During CPU generated transactions, this active-low signal indicates that a bus transaction is active. An external pullup resistor is required. CPU Write Status During CPU generated transactions, this active-low signal indicates whether or not a write is occurring. If a write is not occurring, then the implication is that a read is in progress. CPU Byte Enable Bus During CPU generated transactions, these active-low signals indicate which byte lanes are in use. Note: The table below indicates which cpu_be_n signal corresponds to which byte lane, whether or not the system is in big or little endian mode Data Bits cpu_be_n[0] cpu_be_n[1] cpu_be_n[2] cpu_be_n[3] cpu_ack_n O Not applicable 7:0 15:8 23:16 31:24 cpu_addr[3:2] I Not applicable cpu_ale I Not applicable cpu_cip_n I Not applicable cpu_wr_n I Not applicable cpu_be_n[3:0] I Not applicable CPU Acknowledge During CPU generated transactions, this active-low signal is generated by the RC32134 to indicate that the present data have been accepted. CPU Last Data During CPU generated transactions, this active-low signal indicates during the data phase that the present data is the last data. CPU Bus Error During both CPU and DMA generated transactions, this active-low signal indicates that a bus error has occurred. This signal can also be optionally attached to an interrupt line. Table 2 RC32134 Pin Descriptions (Page 1 of 8) cpu_last_n I Not applicable cpu_buserr_n O Not applicable 5 of 25 April 9, 2001 IDT79RC32134 Pin Name cpu_masterclk I Type Alternate Signal(s) sdram_clk Description CPU Master System Clock Provides the basic system clock. This clock must be the same clock that is provided to the RC32364 and also, if used, to SDRAM. CPU Cold Reset This active-low signal is asserted to the RC32364 CPU and RC32134 after Vcc becomes valid on the initial power-up. The Reset initialization vectors, for both the RC32364 and the RC32134, are latched by cold reset. CPU Warm Reset This active-low signal is a secondary reset signal asserted to the CPU at least 256 clocks after cold reset, allowing, for instance, stabilization of RC32364's PLL. CPU Bus Request This active-low signal requests the CPU bus from the RC32364, for instance, by RC32134 to perform a DMA operation. CPU Bus Grant This active-low signal is a CPU bus grant from the RC32364, indicating that the local CPU bus has been released to the RC32134. CPU Interrupt This active-low signal is an interrupt indication to the CPU from RC32134's Interrupt Controller. Note: This pin is typically hooked up to the CPU's interrupt 3. CPU Direction Transmit/Receive This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during DMA read operations. This signal is tri-stated during CPU accesses (when the CPU owns the bus) and driven during DMA generated accesses. Note: An external pull-up resistor is required. cpu_coldreset_n I Not applicable cpu_reset_n O Not applicable cpu_busreq_n O Not applicable cpu_busgnt_n I Not applicable cpu_int_n O interrupt_n cpu_dt_r_n O mem_245_dt_r_n, sdram_245_dt_r_n, edodram_245_dt_r_n PCI Interface pci_ad[31:0] I/O Not applicable PCI Multiplexed Address/Data Bus This address is driven by the Bus Master during initial frame_n assertion. The Data is then driven by the Bus Master during writes; or the Data is driven by the Bus Slave during reads. PCI Multiplexed Command/Byte Enable Bus The Command bus (active high) is driven by the Bus Master during the initial frame_n assertion. The Byte Enable bus (active low) is driven by the Bus Master during the data phase(s). Note: The table below indicates which cpu_be_n signal corresponds to which byte lane, whether or not the system is in big or little endian mode. Data Bits pci_be[0] pci_be[1] pci_be[2] pci_be[3] pci_par I/O Not applicable 7:0 15:8 23:16 31:24 pci_cbe_n[3:0] I/O Not applicable PCI Parity This signal indicates even parity of the pci_ad[31:0] bus and is driven by the Bus Master during Address and Write Data phases. During the Read data phase, this signal is driven by the Bus Slave. PCI Frame Negated This active-low signal is driven by the Bus Master and indicates the duration of a PCI transfer. Assertion indicates the beginning of a bus transaction. De-assertion indicates the last data. Table 2 RC32134 Pin Descriptions (Page 2 of 8) pci_frame_n I/O Not applicable 6 of 25 April 9, 2001 IDT79RC32134 Pin Name pci_trdy_n Type Alternate Signal(s) I/O Not applicable Description PCI Target Ready Negated This active-low signal is driven by the Bus Slave and indicates that the current data can complete (the bus slave can accept/drive data). PCI Initiator Ready Negated Driven by the Bus Master, this active-low signal indicates that the current data can complete (PCI initiator is ready to accept/drive data). PCI Stop Negated Driven by the Bus Slave this active-low signal terminates the current bus transaction. PCI Initialization Device Select Host mode: pci_req_n[2] is an input indicating a request from an external device. Satellite mode: used as pci_idsel pin which selects this device during a configuration read or write. PCI Parity Error Negated Driven by the receiving Bus Agent 2 clocks after the data is received, if a parity error occurs. System Error Driven by any agent, this active-low signal indicates an address parity error, data parity during a Special Cycle command, or any other system error. An external 2.7K (5V) ohm or 8.2K (3.3V) ohm pullup resistor is required, per the PCI revision 2.1 specifications. PCI Clock Clock for PCI bus transactions that uses the rising edge for all timing references. Note that the PCI clock does not need to be synchronized to the cpu_masterclk. PCI Reset Negated In Host mode, this active-low signal resets all PCI related logic. In Satellite mode, with boot from PCI mode, this signal resets all PCI related logic and also asserts the warm reset, cpu_rst_n, to the RC32134. and the RC32364. PCI Device Select Negated This active-low signal is driven by the target to indicate that the target has decoded the present address as a target address. PCI Bus Request #2 Negated This is an active-low signal that in Host mode is an input indicating a request from an external device. In Satellite mode pci_req_n[2] is used as the pci_idsel pin, which selects this device during a configuration read or write. PCI Bus Request #1 Negated In Host mode, pci_req_n[1] is an input indicating a request from an external device. In Satellite mode pci_req_n[1] is unused. PCI Bus Request #0 Negated In Host mode, this active-low signal is an input indicating a request from an external device. In Satellite mode, pci_req_n[0] is an output indicating a request from this device. PCI Bus Grant #2 Negated In Host mode, this active-low signal is an output indicating a grant to an external device. In Satellite mode, pci_gnt_n[2] is used as the pci_inta_n output pin. An external 5k ohm pull-up resistor is required, per the PCI revision 2.1 specifications. Note: In host mode, int_n[1] on the RC32364 can be used for a pci_inta_n input and pci_int[d:c:b]_n uses int_n[5:4:2] on the RC32364 Bus Interface. pci_gnt_n[1] O pci_eeprom_cs PCI Bus Grant #1 Negated In Host mode, this active-low signal is an output indicating grants to external devices. In Satellite mode, pci_gnt_n[1] is used as the pci_eeprom_cs output pin for Serial Chip Select, for loading PCI Configuration Registers in the RC32134 Reset Initialization Vector PCI boot mode. Table 2 RC32134 Pin Descriptions (Page 3 of 8) pci_irdy_n I/O Not applicable pci_stop_n pci_idsel I/O I Not applicable pci_req_n[2] pci_perr_n pci_serr_n I/O I/O Not applicable Not applicable pci_clk I Not applicable pci_rst_n I Not applicable pci_devsel_n I/O Not applicable pci_req_n[2] I pci_idsel pci_req_n[1] I Not applicable pci_req_n[0] I/O Not applicable pci_gnt_n[2] O pci_inta_n 7 of 25 April 9, 2001 IDT79RC32134 Pin Name pci_gnt_n[0] Type Alternate Signal(s) I/O Not applicable Description PCI Bus Grant #0 Negated In Host mode, this active-low signal is an output indicating a grant to an external device. In Satellite mode, pci_gnt_n[0] is an input indicating a grant to this device. PCI Interrupt #A Negated In Host mode,pci_gnt_n[2] is an output indicating a grant to an external device. In Satellite mode, pci_gnt_n[2] is used as the pci_inta_n output pin. An external pull-up is required, per the PCI revision 2.1 specifications. Note: In host mode, int_n[1] on the RC32364 can be used for a pci_inta_n input and pci_int[d:c:b]_n uses int_n[5:4:2] on the RC32364 Bus Interface. pci_lock_n I Not applicable PCI Lock Negated This active-low signal is driven by the Bus Master and indicates that an exclusive operation is occurring. PCI EEPROM Master Data Out In Serial mode, this signal is an output pin from RC32134 that connects as an Input to a Serial Chip for the Serial data input stream. In PCI satellite mode, it is an output pin from RC32134 that connects as an Input to a Serial Chip for the Serial data input stream for loading PCI Configuration Registers in the RC32134 Reset Initialization Vector PCI boot mode. This pin is also multiplexed as a PIO pin. PCI EEPROM Master Data In The Serial mode provides an input pin to RC32134 from the Output of a Serial Chip for the Serial data output stream. The PCI satellite mode provides an input pin to RC32134 from the Output of a Serial Chip for the Serial data output stream, for PCI Configuration Registers in the RC32134 Reset Initialization Vector PCI boot mode. This pin is also multiplexed as a PIO pin. PCI EEPROM Chip Select Host mode: pci_gnt_n[1] is an output indicating grants to external devices. Satellite mode: Used as pci_eeprom_cs output pin for SPI Chip Select for loading PCI Configuration Registers in the RC32134 Reset Initialization Vector PCI boot mode. PCI EEPROM Serial Clock Serial mode: Output pin for Serial Clock. PCI satellite mode: Output pin for Serial Clock for loading PCI Configuration Registers in the RC32134 Reset Initialization Vector PCI boot mode. This pin is also multiplexed as a PIO pin. pci_inta_n I/O pci_gnt_n[2] pci_eeprom_mdo I/O pio[11] pci_eeprom_mdi I/O pio[8] pci_eeprom_cs I/O pci_gnt_n[1] pci_eeprom_sk I/O pio[10] Memory/I/O Controller mem_addr[22:2] I/O edodram_addr[15:2] sdram_addr[15:13] sdram_addr[11:2] Memory Address Bus These signals provide the Memory or DRAM address, during a Memory or DRAM bus transactiion. During each word data, the address increments either in linear or sub-block ordering, depending on the transaction type. For 32-bit system, use mem_addr[3:2] for the least significant address bits [3:2]. For 8 or 16-bit wide ports, to provide the least significant address bits [3:0], use cpu_addr[3:2] and cpu_be_n[1:0]. mem_addr subsets mem_addr[22:20] mem_addr[15:2] I/O I/O reset_boot_mode[1:0] reset_pci_host_mode sdram_addr[15:13] sdram_addr[11:2] edodram_addr[15:2] mem_cs_n[5:0] O Not applicable Memory Chip Select Negated This active-low signal indicates that a Memory or I/O Bank is actively selected. Table 2 RC32134 Pin Descriptions (Page 4 of 8) 8 of 25 April 9, 2001 IDT79RC32134 Pin Name mem_oe_n Type Alternate Signal(s) O Not applicable Description Memory Output Enable Negated This active-low signal indicates that either a Memory or I/O Bank can output its data lines onto the cpu_ad bus. Memory Write Enable Negated Bus These active-low signals indicate which bytes are to be written during a memory or I/O transaction. Memory Wait Negated In MEM, IOI, IOM modes this active-low signal allows external wait-states to be injected during the last cycle before data is sampled. In DPM (dual-port) mode, this signal allows dual-port busy signal to restart memory transaction. Memory FCT245 Output Enable Negated This active-low signal controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to a memory or I/O bank. Memory FCT245 Direction Xmit/Rcv Negated Uses the cpu_dt_r_n pin. mem_we_n[3:0] mem_wait_n O I Not applicable edo_dram_wait_n mem_245_oe_n O Not applicable mem_245_dt_r_n EDODRAM Controller edodram_addr[15:2] O cpu_dt_r_n O mem_addr[15:2] Edodram_addr/sdram_addr mode These are output signals that provide a DRAM address during a DRAM transaction. The DRAM address multiplexes between Row and Column Addresses. During each word data, the column address increments either in linear or sub-block ordering, depending on the type of transaction. Allows an external memory debug emulator to inject wait-states. For more detail, see the user's manual. DRAM Row Address Strobe Negated Bus SDRAM mode: Provides chip select to each SDRAM bank. EDODRAM mode: Used as edodram_ras_n[3:0] pins to provide a RAS signal for each EDODRAM bank. DRAM Column Address Strobe Negated Bus In the EDODRAM mode these signals are used as edodram_cas_n[3:0] to provide a CAS signal for each byte lane. In the SDRAM mode, these signals provide byte enables for each byte lane of all DRAM banks. DRAM EDO Output Enable Negated In the EDODRAM mode, this active-low signal provides an output enable signal for reads for particular OE types of EDODRAM. This signal also controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. This signal also controls the output enable to each EDO DRAM chip. Alternatively, because the EDODRAM controller always uses Early Writes and CAS controlled non-interleaved Reads, the OE_n pin, on each EDO DRAM chip, can simply be tied to ground. The SDRAM RAS mode is a control signal to all SDRAM banks. In SDRAM mode, this signal controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. DRAM EDO Write Enable Negated In EDODRAM mode, this active-low signal is used as the edodram_we_n pin to provide a write enable signal for EDODRAM. Write enable is valid at all times and high during refresh. In SDRAM mode, this signal provides the SDRAM WE control signal to all SDRAM banks. DRAM Wait Negated In the EDO DRAM mode, this active-low signal allows external wait-states to be injected at any time during the EDO DRAM cycle. In the MEM, IOI, IOM modes, this active-low signal allows external wait-states to be injected during the last cycle before data is sampled. The DPM (dual-port) mode allows the dual-port busy signal to restart memory transactions. Table 2 RC32134 Pin Descriptions (Page 5 of 8) edodram_ras_n[3:0] O sdram_cs_n[3:0] edodram_cas_n[3:0] O sdram_bemask_n[3:0] edodram_oe_n O sdram_ras_n, sdram_245_oe_n edodram_we_n O sdram_we_n edodram_wait_n I mem_wait_n 9 of 25 April 9, 2001 IDT79RC32134 Pin Name edodram_245_oe_n Type Alternate Signal(s) O sdram_245_oe_n Description DRAM FCT245 Output Enable Negated In the SDRAM mode this active-low signal controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. In the EDODRAM mode this signal controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. This signal also controls the output enable to each EDO DRAM chip. Alternatively, because the EDODRAM controller always uses Early Writes and CAS controlled non-interleaved Reads, the OE_n pin, on each EDO DRAM chip, can simply be tied to ground. DRAM/Mem FCT245 Direct Xmit/Rcv Negated This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during DMA read operations. This signal is tri-stated during CPU accesses (when the CPU owns the bus) and drives during DMA generated accesses. edodram_245_dt_r_n O cpu_dt_r_n SDRAM Controller Interface sdram_addr[15:13] sdram_addr[11:2] O mem_addr[15:13] mem_addr[11:2] SDRAM Address Bus These signals are outputs providing a DRAM address during a DRAM transaction. The DRAM address multiplexes between Row and Column Addresses. During each word data, the column address increments either in linear or sub-block ordering, depending on the type of transaction. SDRAM Address line 12 This SDRAM address is dedicated to the SDRAM and multiplexes between the row address; and during the precharge command, the "all bank" indicator. SDRAM RAS Negated SDRAM mode: Provides SDRAM RAS control signal to all SDRAM banks. EDODRAM mode: Provides an output enable signal for reads for particular OE types of EDODRAM. SDRAM CAS Negated This active-low signal provides an SDRAM CAS control signal to all SDRAM banks. SDRAM WE Negated SDRAM mode: Provides SDRAM WE control signal to all SDRAM banks. EDODRAM mode: Used as edodram_we_n pin to provide a write enable signal for EDODRAM. Write enable is valid at all times and high during refresh. SDRAM Clock This signal provides the basic system clock and must be the same clock that is provided to the RC32364 and also, if used, to SDRAM. SDRAM Clock Enable In the SDRAM mode this signal provides the clock enable to all SDRAM banks. SDRAM Chip Select Negated Bus In SDRAM mode, these active-low signals provide chip select to each SDRAM bank. In EDODRAM mode they are used as the edodram_ras_n[3:0] pins and provide a RAS signal for each EDODRAM bank. SDRAM Byte Enable Mask Negated Bus The SDRAM mode provides byte enables for each byte lane of all DRAM banks. To provide a CAS signal for each byte lane, the EDODRAM mode is used as edodram_cas_n[3:0]. SDRAM FCT245 Output Enable Negated In SDRAM mode, this active-low signal controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. In EDODRAM mode this signal controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. Also controls output enable to each EDO DRAM chip. Alternatively, because the EDODRAM controller always uses Early Writes and CAS controlled non-interleaved Reads, the OE_n pin on each EDO DRAM chip can simply be tied to ground. Table 2 RC32134 Pin Descriptions (Page 6 of 8) sdram_addr_12 O PIO[9] sdram_ras_n O edodram_oe_n sdram_cas_n sdram_we_n O O Not applicable edodram_we_n sdram_clk I cpu_masterclk sdram_cke sdram_cs_n[3:0] O O Not applicable edodram_ras_n[3:0] sdram_bemask_n[3:0] O edodram_cas_n[3:0] sdram_245_oe_n O edodram_245_oe_n, edodram_oe_n 10 of 25 April 9, 2001 IDT79RC32134 Pin Name sdram_245_dt_r_n Type Alternate Signal(s) O cpu_dt_r_n Description SDRAM FCT245 Direction Transmit/Receive This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank and is asserted during DMA read operations. This signal is tri-stated during CPU accesses (when the CPU owns the bus) and drives during DMA generated accesses. DMA Interface dma_ready_n[1:0] I/O dma_done_n[1:0] pio[1:0] DMA Ready Negated Bus Input pin for general purpose DMA channels[1:0] that can initiate the next datum in the current DMA descriptor frame. dma_ready_n[1:0] pins are not synchronized internally by the RC32134 and thus must meet the specified setup and hold time with respect to the input clock. DMA Done Input pin for general purpose DMA channels[1:0] that can terminate the current DMA descriptor frame. dma_done_n[1:0] I/O dma_ready_n[1:0] Interrupt Controller interrupt_n I/O cpu_int_n Interrupt Negated Uses cpu_int_n. This active-low signal is an interrupt indication to the CPU from RC32134's Interrupt Controller. PIO Interface pio[11:0] I/O pci_eeprom_mdo pci_eeprom_sk sdram_addr_12 pci_eeprom_mdi uart _rx[0], uart_tx[0] uart_rx[1], uart_tx[1] timer_tc_n[0], timer_tc_n[1] dma_ready_n[0] dma_ready_n[1] Programmable Input/Output General purpose pins that can each be configured as a general purpose input or general purpose output. The pci_eeprom_mdo, pci_eeprom_sk, and sdram_addr12 default to outputs. The rest default to inputs. Timer/Counter timer_tc_n[1:0] timer_gate_n[1:0] UART Interface uart_rx[1:0] uart_tx[1:0] I/O I/O pio[7] pio[5] pio[6] pio[4] UART Receive Data Bus UART mode: Each UART channel receives data on their respective input pin. UART Transmit Data Bus UART mode: Each UART channel sends data on their respective output pin. Note that these pins default to inputs at reset time and must be programmed via the PIO interface before being used as UART outputs. Table 2 RC32134 Pin Descriptions (Page 7 of 8) O I timer_gate_n[1:0], pio[3:2] timer_tc_n[1:0], pio[3:2] Timer Terminal Count Overflow Negated Output indicating that the timer has reached its count compare value and has overflowed back to 0. Timer Gate Negated Input indicating that the timer may count one tick on the next clock edge. 11 of 25 April 9, 2001 IDT79RC32134 Pin Name Reset reset_boot_mode[1:0] I/O mem_addr[22:21] Reset Initialization Vector Used as Reset Initialization. Vector input pins that are latched by coldreset_n de-asserting. Value 11 10 01 Description Non-boot mode. Idle at reset. This RC32134 does not supply boot code control. Reserved. PCI-boot mode. (pci_host_mode must be in satellite mode). RC32134 will reset either from a cold reset or from a PCI reset. Boot code is provided via PCI. Standard-boot mode. Boot from this RC32134's memory controller (typical system). Type Alternate Signal(s) Description 00 reset_pci_host_mode I/O mem_addr[20] Reset PCI Host Mode Used as Reset Initialization. Vector input pins that are latched by coldreset_n de-asserting. Programming for this signal is as indicated below: Value 1 0 Description PCI is in satellite mode. PCI is in host mode (typical system). JTAG jtag_tck I Not applicable JTAG Test Clock Provides clock for boundary scan test cells. Note: Must be either dynamically driven or an external pull-up or pull-down resistor is required, if JTAG is not being used. JTAG Test Mode This signal provides command/mode input for boundary scan test cells. An external pull-up resistor is required. JTAG Test Data Input Provides data input for boundary scan test cells. An external pull-up resistor is required. JTAG Test Data Out Provides data output for boundary scan test cells. JTAG Test Reset Negated This active-low signal provides reset to boundary scan test cells. Note: An external pull-up resistor is required. This pin must be driven low to reset the JTAG tap controller, or held low if JTAG is not being used. Table 2 RC32134 Pin Descriptions (Page 8 of 8) jtag_tms I Not applicable jtag_tdi jtag_tdo jtag_trst_n I O I Not applicable Not applicable Not applicable 12 of 25 April 9, 2001 IDT79RC32134 Logic Diagram -- RC32134 cpu_[31:0] cpu_addr[3:2] cpu_ale cpu_cip_n cpu_wr_n cpu_be_n[3:0] cpu_ack_n cpu_last_n cpu_buserr_n cpu_masterclk cpu_coldreset_n cpu_reset_n cpu_busreq_n cpu_busgnt_n cpu_int_n[3] cpu_dt_r_n pci_cbe_n[3:0] pci_ad[31:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[2] pci_req_n[1] pci_req_n[0] pci_gnt_n[2] pci_gnt_n[1] pci_gnt_n[0] pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_mdo pci_eeprom_cs pci_eeprom_sk Local Memory /Bus Interface Local Memory / Bus Interface mem_addr[22:2] mem_addr[2:2] mem_cs_n[5:0] mem_oe_n mem_we_n[3:0] mem_wait_n mem_245_oe_n mem_245_dt_r_n edodram_addr[15:2] edodram_ras_n[3:0] edodram_cas_n[3:0] edodram_oe_n edodram_we_n EDODRAM / SDRAM Controller edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n sdram_addr[15:13] PCI Interface RC32134 Logic Symbol sdram_addr[11:2] sdram_ras_n sdram_cas_n sdram_we_n sdram_clk sdram_cke sdram_cs[3:0] sdram_bemask_n[3:0] sdram_245_oe_n sdram_245_dt_r_n sdram_addr_12 dma_ready_n[1:0] timer_tc_n[1:0] Interrupt Interface interrupt_n jtag_tck jtag_tms jtag_tdi jtag_tdo jtag_trst_n reset_boot_mode reset_pci_host_mode Gnd Gnd JTAG Interface uart_rx[1:0] uart_tx[1:0] pio[11:0] Power/ Ground Vcc to IO Vcc to core Vcc IO Vcc core Note: The alternate signals are listed in "RC32134 Alternate Signal Functions" on page 22 13 of 25 PIO Interface Reset UART Timer DMA Interface Memory & I/O Bus Controllers April 9, 2001 IDT79RC32134 Clock Parameters -- RC32134 (Tc = 0C to +90C Commercial, Tc = -40C to +90C Industrial, Vcc Core = +3.3V5%) RC32134 75MHz Min cpu_masterclock HIGH cpu_masterclock LOW cpu_masterclock period cpu_masterclock Rise& Fall Time pci_clk Period pci_clk Rise& Fall Time jtag_tck Rise& Fall Time jtag clock period tMCHIGH tMCLOW tMCP Parameter Symbol Test Conditions Transition 3ns Transition 3ns Units Max -- -- -- 3 -- 3 5 -- ns ns ns ns ns ns ns ns 6 6 13.33 -- 30 tMCRise, tMCFall tPCP tPCRise, tPCFall tJCRise, tJCFall jtag_clk PCI 2.1 -- -- 100 VCC cpu_masterclk (MClk) cpu_coldreset_n cpu_reset*(internal signal) modebit[9:0] >= 150 ms >= 10 ms >= 64 MClk cycles Figure 2 Mode Configuration Interface Reset Sequence There is no special requirement for how fast Vcc ramps up to 3.3V. However, all timing references are based on Vcc stabilized at 3.3V + 5%. 14 of 25 April 9, 2001 IDT79RC32134 AC Timing Characteristics -- RC32134 (Tc = 0C to +90C Commercial, Tc = -40C to +90C Industrial, Vcc Core = +3.3V5%) Signal Local Memory/ Peripheral Bus cpu_ad[31:0] (address phase), cpu_addr[3:2] cpu_ad[31:0] (address phase), cpu_addr[3:2] cpu_ad[31:0] (data phase) cpu_ad[31:0] (data phase) cpu_ale rising cpu_ale falling (ale pulse width) cpu_busgnt_n, cpu_wr_n, cpu_be_n[3:0], cpu_last_n Tsu1 Thld1 Tsu2 Thld2 Tsu3 Tale high Tsu4 cpu_ale falling cpu_ale falling cpu_masterclk rising cpu_masterclk rising cpu_masterclk falling cpu_ale rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising 3 3 5.5 0.7 0 4 5 0.7 5 0.7 -- -- -- -- 11 0.5 -- -- -- -- -- -- -- -- -- -- 8 8 8 8 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Chapter 3, Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 5.4 Figure 8.8 Figure 8.9 Symbol Reference Edge 75MHz Min Max Unit User Manual Timing Diagram Reference cpu_busgnt_n, cpu_wr_n, cpu_be_n[3:0], cpu_reset_n, cpu_last_n Thld4 cpu_cip_n cpu_cip_n cpu_ack_n, cpu_buserr_n, cpu_reset_n cpu_busreq_n, cpu_int_n cpu_dt_r_n cpu_ad[31:0] cpu_ad[31:0] output hold time cpu_ack_n, cpu_buserr_n, cpu_reset_n, cpu_busreq_n, cpu_int_n DMA dma_ready_n[1:0], dma_done_n[1:0] dma_ready_n[1:0], dma_done_n[1:0] Memory-I/O Controller mem_wait_n mem_wait_n mem_addr[22:2] mem_cs_n[5:0] mem_oe_n, mem_we_[3:0], mem_245_dt_r_n, mem_245_oe_n mem_addr[22:2] mem_cs_n[5:0] mem_oe_n, mem_we_[3:0], mem_245_dt_r_n, mem_245_oe_n Tsu6 Thld8 Tdo5 Tdo6 Tdo7 Tdoh3 Tsu7 Thld9 Tsu5 Thld5 Tdo1 Tdo2 Tdo3 Tdo4 Tdoh1 Tdoh2 cpu_masterclk rising cpu_masterclk rising 3 0.5 -- -- ns ns Chapter 9, Figures 9.6 & 9.7 cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising 3 0.5 -- -- -- 0.5 -- -- 8 8 8 -- ns ns ns ns ns ns Chapter 3, Figure 3.6 Figure 3.7 Figure 3.8 15 of 25 April 9, 2001 IDT79RC32134 Reference Edge 75MHz Min Max User Manual Timing Diagram Reference Signal PCI Symbol Unit pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, T_su pci_irdy_n, pci_stop_n, pci_idse, pci_perr_n, pci_serr_n, pci_rst_n, pci_devsel_n, pci_lock_n pci_gnt_n[0] pci_req_n[2:0] T_su(ptp) T_su(ptp) pci_clk rising 7 -- ns 10 12 pci_clk rising 0 -- -- -- ns ns ns Note: Refer to PCI Specification, Revision 2.1 for a detailed timing diagram. pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, T_h pci_irdy_n, pci_stop_n, pci_idse, pci_perr_n, pci_serr_n, pci_rst_n, pci_devsel_n, pci_req_n[2], pci_req_n[1], pci_req_n[0], pci_gnt_n[0], pci_lock_n pci_eeprom_mdi pci_eeprom_mdi pci_eeprom_mdo, pci-eeprom_cs pci_eeprom_sk pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n, pci_inta_n, pci_lock_n pci_req_n[0], pci_gnt_n[2:0] SDRAM Controller sdram_245_dt_r_n, sdram_addr[15:2] sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_bemask_n[3:0] sdram_cke sdram_addr_12 sdram_245_oe_n sdram_245_dt_r_n, sdram_addr[15:2] sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_bemask_n[3:0] sdram_cke sdram_addr_12 sdram_245_oe_n EDODDRAM Controller edodram_wait_n edodram_wait_n edodram_addr[15:2], edodram_245_dt_r_n edodram_ras_n[3:0], edodram_cas_n[3:0], edodram_we_n, edodram_oe_n edodram_245_oe_n Tsu7 Thld8 Tdo12 Tdo13 Tdo14 Tdo8 Tdo9 Tdo10 Tdo11 Tdoh4 Tdoh4 Tsu Thld Tp Tp T_val pci_clk rising, 10 pci_eeprom_sk falling pci_clk rising, 10 pci_eeprom_sk falling pci_clk rising, pci_eeprom_sk falling pci_clk rising pci_clk rising 2 10 12 11 ns ns ns ns ns T_val(ptp) pci_clk rising 2 12 ns cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising -- -- -- -- 1 1 8 8 8 8 -- -- ns ns ns ns ns ns Chapter 4, Figure 4.4 11 cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising 3 0.5 -- -- -- -- -- 8 8 8 ns ns ns ns ns Chapter 5, Figure 5.3 16 of 25 April 9, 2001 IDT79RC32134 Reference Edge cpu_masterclk rising 75MHz Min 11 Max -- User Manual Timing Diagram Reference Chapter 5, Figure 5.3 (Continued) Signal edodram_addr[15:2], edodram_245_dt_r_n edodram_ras_n[3:0], edodram_cas_n[3:0], edodram_we_n, edodram_oe_n edodram_245_oe_n Timer timer_tc_n[1:0], timer_gate_n[1:0] timer_tc_n[1:0], timer_gate_n[1:0] timer_tc_n[1:0], timer_gate_n[1:0] timer_tc_n[1:0], timer_gate_n[1:0] PIO PIO[11:0] PIO[11:0] PIO[11], PIO[9:0] PIO[10] PIO[11], PIO[9:0] PIO[10] UARTs uart_rx[1:0], uart_tx[1:0] uart_rx[1:0], uart_tx[1:0] uart_rx[1:0], uart_tx[1:0] uart_rx[1:0], uart_tx[1:0] Interrupt Handling interrupt_n interrupt_n Reset reset_boot_mode, reset_pci_host_mode reset_boot_mode, reset_pci_host_mode JTAG Interface jtag_tms, jtag_tdi, jtag_trst_n jtag_tms, jtag_tdi, jtag_trst_n jtag_tdo Symbol Tdoh5 Unit ns Tsu8 Thld10 Tdo15 Tdoh6 cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising 3 0.5 -- 11 -- -- 8 -- ns ns ns ns Chapter 10, Figures 10.6 and 10.7 Tsu7 Thld9 Tdo16 Tdo19 Tdoh7 Tdoh7 cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising 3 0.5 -- -- 11 11 -- -- 10 12 -- -- ns ns ns ns ns ns Chapter 9, Figures 9.6 and 9.7 Tsu9 Thld11 Tdo16 Tdoh8 cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising 10 10 -- 11 10 -- ns ns ns ns Chapter 11, Figure 11.15 Tdo2 Tdoh2 cpu_masterclk rising cpu_masterclk-rising -- 11 8 -- ns ns Chapter 8, Figures 8.8 and 8.9 Tsu8 Thld12 cpu_masterclk-rising cpu_masterclk-rising 3 0.5 ns ns Chapter 2, Figure 2.6 Tsu Thld Tdo18 jtag_tck rising jtag_tck rising jtag_tck falling 10 10 -- 10 ns ns ns Refer to Figure 2 below Note: Tsux = input setup time to RC32134 Thldx = input hold time to RC32134 Tdox = output propagation time from RC32134 Tdohx = output hold time from RC32134 17 of 25 April 9, 2001 IDT79RC32134 t TC K JTAG _TC K t3 t1 t2 t5 JTA G _TD I/ JTAG _TM S T su JTA G _TD O T do Notes to diagram: t1 = tTCKlow t2 = tTCKHIGH t3 = tTCKFALL t4 = TRST (reset pulse width) t5 = tTCKRise T hld JT AG _TRST t4 > = 25 ns Figure 3 Standard JTAG timing Output Loading for AC Testing (for non-PCI signals) VREF +1.5V - + CLD To Device Under Test Signal All Signals 50 pF Cld Note: PCI pins have been correlated to PCI 2.1. Recommended Operation Temperature and Supply Voltage Grade Commercial Industrial Temperature 0C to +90C (Case) -40 + 90C (Case) Gnd 0V 0V 3.3V5% 3.3V5% VccIO VccCore 3.3V5% 3.3V5% Capacitive Load Deration Refer to the IDT document "RC32134 IBIS Model" under sub-category RC32134 Integrated Processor on the company's web page for Processors (http://www.idt.com/products/pages/Processors.html) . 18 of 25 April 9, 2001 IDT79RC32134 DC Electrical Characteristics Tc = 0C to +90C Commercial, Tc = -40C to +90C Industrial, Vcc Core = +3.3V5% RC32134 75MHz Minimum LOW Drive Pads VOL VOH VIL VIH HIGH Drive Pads VOL VOH VIL VIH PCI Drive Pads VOL VOH VIL VIH CIN CIN CIN COUT I/OLEAK -- -- -- Maximum 0.4V -- 0.8V 1, 2, 3, 4, 5, 8, 15, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31, 104, 106, 118, 133, 137, 142, 161 |IOUT| = 10.8mA |IOUT| = 7.8mA -- Parameter Pin Numbers Conditions Vcc - 0.4V -- 2.0V -- Vcc + 2.0V 0.4V -- 0.8V 9, 10, 11, 12, 13, 107, 108, 109, 112, 113, 114, 115, 116, 117, 119, 122, 123, 124, 125, 126, 129, 132, 134, 135, 138, 139, 143, 144, 146, 147, 149, 152, 154, 155, 159, 160, 165, 167, 168, 169, 170, 171, 174, 175, 176, 177, 178, 179, 180, 181, 184, 185, 186, 187, 188, 189, 190, 191, 194, 195, 196, 197, 198, 199, 200, 201, 204, 205, 206, 207, 208 35, 39, 42, 43, 45, 48, 49, 50, 51, 52, 53, 54, 55, 56, 60, 61, 62, 63, 64, 65, 66, 67, 70, 71, 72, 73, 74, 75, 77, 80, 81, 82, 83, 84, 85, 86, 87, 90, 91, 92, 93, 94, 95, 96, 97, 100, 101, 102, 103 |IOUT| = 19mA |IOUT| = 15.6mA -- Vcc - 0.4V -- 2.0V -- Vcc + 2.0V 0.4V -- 0.8V 5.5 10pF 12pF 8pF 10pF 20uA |IOUT| = 25mA |IOUT| = 19.5mA -- Vcc - 0.4V -- 2.0V -- 5pf All Except 41, 57 41 57 All output pads All pins -- Per PCI 2.1 Per PCI 2.1 -- Input/Output Leakage Power Consumption--RC32134 Parameter Typical lCC Ptyp RC32134 75MHz 360mA 1.2W Conditions CL = 50pF Ta= 25oC Vcc core = 3.3V Vcc IO = 3.3V cpu_masterclk = 75MHz pci_clk = 33MHz CL = 50pF Ta= 55oC Vcc core = Vcc core Max Vcc IO = 3.47V cpu_masterclk = 75MHz pci_clk = 33MHz Max lCC Pmax 460mA 1.6W 19 of 25 April 9, 2001 IDT79RC32134 Absolute Maximum Ratings Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol VCC Vi Tstg Ta Parameter Supply Voltage Input Voltage Storage Temperature Ambient Temperature Value -0.3 Gnd -40 0 Min 4.0 5.5 125 70 Max V V degrees C degrees C Unit Package Pin-out - 208-PQFP The following table lists the pin numbers and signal names for the RC32134. To maximize pin usage, several pins have alternate functions, as noted in the "Alt" column and described in "RC32134 Alternate Signal Functions" on page 22. Signal names ending with an _n are active when low. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function mem_cs_n[5] mem_cs_n[4] mem_cs_n[3] mem_cs_n[2] mem_cs_n[1] Vcc I/O Vss mem_cs_n[0] mem_oe_n mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] mem_wait_n mem_245_oe_n Vcc I/O Vss dma_ready_n[1] dma_ready_n[0] timer_tc_n[1] timer_tc_n[0] Alt Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 Function pci_ad[26] pci_ad[25] pci_ad[24] pci_cbe_n[3] pci_req_n[2] (Host mode) Vcc I/O Vss pci_ad[23] pci_ad[22] pci_ad[21] pci_ad[20] pci_ad[19] pci_ad[18] pci_ad[17] pci_ad[16] Vcc I/O Vss pci_cbe_n[2] pci_frame_n pci_irdy_n pci_trdy_n Alt Pin 105 106 107 108 Function cpu_wr_n cpu_reset_n cpu_ad[21] cpu_ad[9] cpu_ad[22] Vcc I/O Vss cpu_ad[8] cpu_ad[23] cpu_ad[7] cpu_ad[24] cpu_ad[6] cpu_ad[25] cpu_dt_r_n cpu_ad[5] Vcc I/O Vss cpu_ad[26] cpu_ad[4] cpu_ad[27] cpu_ad[3] Alt Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 Function cpu_coldreset_n cpu_be_n[3] cpu_ad[20] cpu_ad[11] cpu_busreq_n Vcc I/O Vss cpu_addr[2] cpu_ad[10] cpu_addr[3] mem_addr[22] mem_addr[21] mem_addr[20] mem_addr[19] mem_addr[18] Vcc I/O Alt 1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 1 1 1 2 66 67 68 69 3 170 171 172 173 174 175 176 177 Vss mem_addr[17] mem_addr[16] mem_addr[15] mem_addr[14] 2 2 2 2 2 2 70 71 72 73 Table 3: RC32134 208-pin QFP Package Pin-Out (Page 1 of 2) 20 of 25 April 9, 2001 IDT79RC32134 Pin 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Function uart_rx[1] uart_tx[1] uart_rx[0] uart_tx[0] Alt 1 1 1 1 Pin 74 75 76 77 78 79 1 1 1 1 80 81 82 83 84 85 86 87 88 89 90 1 91 92 93 1 94 95 1 96 97 98 99 100 101 102 103 104 Function pci_devsel_n pci_stop_n pci_lock_n pci_perr_n Vcc Core Vss pci_serr_n pci_par pci_cbe_n[1] pci_ad[15] pci_ad[14] pci_ad[13] pci_ad[12] pci_ad[11] Vcc I/O Vss pci_ad[10] pci_ad[9] pci_ad[8] pci_cbe_n[0] pci_ad[7] pci_ad[6] pci_ad[5] pci_ad[4] Vcc I/O Vss pci_ad[3] pci_ad[2] pci_ad[1] pci_ad[0] cpu_int_n[3] 1 Alt Pin 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Function cpu_ad[28] cpu_cip_n cpu_last_n cpu_ad[2] Vcc Core Vss cpu_ad[29] cpu_buserr_n cpu_ad[1] cpu_ad[30] cpu_ale cpu_ack_n cpu_ad[0] cpu_ad[31] Vcc I/O Vss cpu_masterclk cpu_ad[15] cpu_ad[16] cpu_be_n[0] cpu_ad[17] cpu_ad[14] cpu_be_n[1] cpu_ad[18] Vcc I/O Vss cpu_ad[13] cpu_be_n[2] cpu_ad[19] cpu_ad[12] cpu_busgnt_n 1 Alt Pin 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function mem_addr[13] sdram_bemask_n[3] sdram_bemask_n[2] sdram_cs_n[3] Vcc Core Vss sdram_cs_n[2] sdram_cke mem_addr[12] mem_addr[11] mem_addr[10] mem_addr[9] mem_addr[8] mem_addr[7] Vcc I/O Vss mem_addr[6] mem_addr[5] mem_addr[4] mem_addr[3] mem_addr[2] sdram_ras_n sdram_cs_n[1] sdram_cs_n[0] Vcc I/O Vss sdram_bemask_n[1] sdram_bemask_n[0] sdram_cas_n sdram_we_n sdram_245_oe_n 1 2 1 1 2 2 2 2 2 1 1 1 1 2 2 2 2 2 1 Alt 2 1 1 1 Vcc Core Vss pci_eeprom_mdo pci_eeprom_mdi pci_eeprom_sk sdram_addr_12 jtag_trst_n jtag_tck jtag_tms jtag_tdo Vcc I/O Vss jtag_tdi pci_gnt_n[2] (Host mode) pci_rst_n pci_clk pci_gnt_n[1] (Host mode) pci_gnt_n[0] pci_req_n[1] (Host mode) pci_req_n[0] Vcc I/O Vss pci_ad[31] pci_ad[30] pci_ad[29] pci_ad[28] pci_ad[27] Table 3: RC32134 208-pin QFP Package Pin-Out (Page 2 of 2) 21 of 25 April 9, 2001 IDT79RC32134 RC32134 Alternate Signal Functions Pin 14 18 19 20 21 22 23 24 25 28 29 30 31 39 42 44 57 104 118 142 167 168 Alt #1 sdram_wait_n dma_done_n[1] dma_done_n[0] timer_gate_n[1] timer_gate_n[0] pio[5] pio[4] pio[7] pio[6] pio[11] pio[8] pio[10] pio[9] pci_inta_n Satellite NA unused (Satellite) pci_idsel (Satellite) interrrupt_n mem_245_dt_r_N sdram_clk reset_boot_mode[1] reset_boot_mode[0] Alt #2 edodram_wait_n pio[0] pio[1] pio[2] pio[3] NA NA NA NA NA NA NA NA NA pci_eeprom_cs (Satellite ) NA NA NA sdram_245_dt_r_n NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA edodram_245_dt_r_n NA NA NA Alt #3 Pin 169 179 180 181 184 186 187 188 189 190 191 194 195 196 197 198 199 200 201 207 208 Alt #1 reset_pci_host_mode edodram_cas_n[3] edodram_cas_n[2] edodram_ras_n[3] edodram_ras_n[2] edodram_addr[12] sdram_addr[11] sdram_addr[10] sdram_addr[9] sdram_addr[8] sdram_addr[7] sdram_addr[6] sdram_addr[5] sdram_addr[4] sdram_addr[3] sdram_addr[2] edodram_oe_n edodram_ras_n[1] edodram_ras_n[0] edodram_we_n edodram_245_oe_n NA NA NA NA NA NA edodram_addr[11] edodram_addr[10] edodram_addr[9] edodram_addr[8] edodram_addr[7] edodram_addr[6] edodram_addr[5] edodram_addr[4] edodram_addr[3] edodram_addr[2] NA NA NA NA edodram_oe_n Alt #2 Alt #3 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 22 of 25 April 9, 2001 IDT79RC32134 Package Drawing - 208-pin PQFP 23 of 25 April 9, 2001 IDT79RC32134 Package Drawing - page two 24 of 25 April 9, 2001 IDT79RC32134 Ordering Information IDT79RCXX Product Type V Operating Voltage DDD Device Type PP Package T Temp range/ Process blank = Commercial Temperature (0C to +90C Case) I = Industrial Temperature (-40C to +90C Case) DS = 208-pin PQFP 134 = 32134 System Controller V = 3.3V 5% IDT79RC32 = 32-bit family product Valid Combinations IDT79RC32V134 DS IDT79RC32V134 DSI 208-pin PQFP package - Commercial Temperature 208-pin PQFP package - Industrial Temperature CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com for Tech Support: email: rischelp@idt.com phone: 408-492-8208 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 25 of 25 April 9, 2001 |
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